The present embodiments relate to electronic devices and circuits and are more particularly directed to such devices and circuits that include a first-in first-out (“FIFO”) circuit with overflow protection.
Electronic circuits have become prevalent in numerous applications, including uses for devices in personal, business, and other environments. Demands of the marketplace affect many aspects of the design of these circuits, including factors such as device complexity, size, and cost. Various of these electronic circuits include some aspect of digital signal processing and, quite often, these circuits include storage devices that operate on a FIFO basis. As is well-known in the art, such FIFO circuits are so named because data words are read from the circuit in the same order as they were written to the circuit. Word size of the FIFO depends on the application and may be any number of bits, where 4 bits, 8 bits, 16 bits, and 32 bits are common examples, while any number of bits per word may be implemented based on the application. The number of words in a given FIFO also is typically dictated at least in part by the application.
Given that a FIFO storage circuit has a limited storage size, provisions have been made in the prior art in case of an overflow condition in the FIFO. Such an overflow occurs when a data word is received or otherwise scheduled to be written into the FIFO, yet the writing of that word would overwrite valid data in the FIFO that has not yet been read. In other words, were such a word written into the FIFIO, it would overwrite and thereby destroy valid data. In the prior art, when such a potential overflow is detected, then some type of intervention has been employed. A common response is to prevent the write, which would otherwise overwrite valid unread data, while also generating an interrupt to some type of controller or other responsive circuit. In this way, the responsive circuit can deny the receipt of any additional words while also holding the FIFO write in abeyance until a read from the FIFO occurs, thereby freeing a word slot in the FIFO to receive the pending write. Alternatively, the interrupt may require a more intrusive response by the device, such as a system reset. Without these types of intervention, valid data in the FIFO can be overwritten and thereby provide erroneous results that are derived from the newer data as opposed to the older yet valid data that was overwritten.
In addition to the interrupt-type response described above, another approach made in the prior art to minimize FIFO overflow conditions is through the design sizing of the FIFO. For example, one approach is to determine the maximum number of words that will require storage in the FIFO for some large percentage of the time, such as 95 percent of the time. For example, assume a design implementation where it is anticipated that a FIFO will require storage of no more than 32 words over 95 percent of the time. Then, to finalize the actual implemented size of the FIFO, the maximum number is doubled to define the actual number of words that can be accommodated by the FIFO. Thus, continuing the example of 32 words, that number is doubled so that the FIFO is constructed to store up to 64 words. In this manner, for that 5 percent of the time not contemplated in the preceding, it is assumed that no more than the doubled value, 64 words, will be required to be stored in the FIFO. Thus, if during the 5 percent of the time up to 64 words require storage, the FIFO is still sufficiently large so as to provide storage for those words. However, if that upper limit (e.g., 64 words) is sought to be exceeded by a write at any given time, then a response such as the above-described interrupt process may also be implemented in connection with the FIFO.
While the above-described approaches have proven workable in various implementations, the present inventor has observed that the prior art may include various drawbacks. For example, in the prior art approach of doubling the FIFO space, an inefficiency is necessarily provided in that, for potentially a majority of the time, up to one-half of the FIFO will remain unwritten with valid data. This unoccupied space corresponds to increased area used in a circuit such as an integrated circuit. Additionally, there may be increased power consumption or considerations with respect to this enlarged FIFO. As yet another and often key consideration, doubling of the FIFO space increases device cost, which is commonly a restrictive drawback in the commercial marketplace. As another example, a smaller FIFO that is forced to often reset or interrupt due to repeated overflow conditions may be too restrictive for various applications. Thus, the preferred embodiments as set forth below seek to improve upon the prior art as well as these associated drawbacks.